1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device having a MOS transistor. More particularly, the present invention relates to a semiconductor integrated circuit device provided with a means for preventing a backflow current in a MOS transistor.
2. Description of the Prior Art
Some semiconductor integrated circuit devices incorporate a P-channel MOS transistor Q5 having a supply voltage VDD applied to the source and backgate thereof as shown in FIG. 4. In this MOS transistor Q5, a parasitic diode D5 is formed from the drain to the backgate.
As a result, when the MOS transistor Q5 is reversely biased, and a voltage higher than the forward voltage of the parasitic diode is applied between the source and drain, the parasitic diode D5 turns on, and a backflow current flows through the parasitic diode D5.
Various semiconductor integrated circuit devices have conventionally been proposed that are provided with a means for preventing such a backflow current. For example, in the regulator shown in FIG. 5, between, at one end, the conducting terminal t1 and backgate of a P-channel MOS transistor Q1 serving as an output transistor and, at the other, a power supply terminal 1 to which a supply voltage VDD is applied, there is provided a P-channel MOS transistor Q2 that functions as a power supply shut-off switch. The conducting terminal t4 of the MOS transistor Q2 is connected to the power supply terminal 1, and the conducting terminal t3, backgate, and gate of the MOS transistor Q2 is connected to the conducting terminal t1 and backgate of the MOS transistor Q1. The conducting terminal t2 of the MOS transistor Q1 is connected to an output terminal 2. In the regulator shown in FIG. 5, when a voltage higher than the supply voltage VDD is applied from outside to the output terminal 2, the MOS transistor Q2 turns off, and this prevents a backflow current.
On the other hand, in the output stage circuit proposed in Japanese Patent Application Laid-Open No. H10-341141, between, at one end, the conducting terminal and backgate of a P-channel MOS output transistor and, at the other, a power supply terminal to which an external supply voltage is applied, there is provided a power supply shut-off switch so that, when a supply voltage monitoring circuit recognizes a drop in the supply voltage, the power supply shut-off switch is turned off, and this prevents a backflow current.
However, in the regulator shown in FIG. 5, since the gate and conducting terminal t3 of the MOS transistor Q2 are connected together, in normal operation (the operation performed when the supply voltage VDD is higher than the voltage VOUT at the output terminal 2), it is impossible to make the voltage between the gate and conducting terminal t4 of the MOS transistor Q2 sufficiently high, and thus, in normal operation, the voltage between the conducting terminals t3 and t4 of the MOS transistor Q2 is high. This means that the on-state resistance of the MOS transistor Q2 is high in normal operation. This makes it impossible to reduce the voltage loss in normal operation.
On the other hand, in the output stage circuit proposed in Japanese Patent Application Laid-Open No. H10-341141, no consideration is given at all to the on-state resistance of the power supply shut-off switch. This makes it impossible, in a case where the on-state resistance of the power supply shut-off switch is high, to reduce the voltage loss in normal operation (the operation performed when the external supply voltage is higher than a predetermined level).